The present invention relates to a logic circuit in a semiconductor integrated circuit chip. More particularly, the present invention relates to a selector circuit having an operation speed not affected by the number of selections from which the selector circuit must select.
When a logic circuit operating as a selector circuit is made by using MOS transistors, a conventional practice is to implement the selector circuit using the circuit, illustrated in FIG. 1.8 on page 12 of "Principle of CMOS VLSI design," published by Maruzen Company Ltd. on Aug. 30, 1988, or a circuit in FIG. 1.10 on page 14 of the same book. These circuits are illustrated in FIGS. 3 and 4 of the present application.
In the circuit illustrated in FIG. 3, setting A to a high level and C to a low level causes a signal which has inverted a signal input to B to be output at F whatever the state of a signal input to D. Setting A to a low level and C to a high level causes a signal which has inverted a signal input to D to be output at F regardless of the state of a signal input to B. Hence, this circuit can be used as a selector circuit that selects one of two signals B and D with the signals A and C as control signals.
The circuit illustrated in FIG. 4 uses a complementary switch having N- and P-type transistors. In this circuit, setting S to a high level and S bar to a low level causes a signal input to A to be output whatever the state of a signal input to B. Setting S to a low level and S bar to a high level causes a signal input to B to be output whatever the state of the signal input to A. Thus, this circuit, too, can be used as a selector circuit that selects one of two signals A and B with signals S and S bar as control signals.
Although the above-described circuits poses no problem when used as a selector circuit to choose one of two signals, these conventional selector circuits have a drawback that the circuit speed decreases significantly as the number of choices increases.
When, for example, a selector circuit designed to select one of four signals is made by expanding the circuit of FIG. 3, a circuit illustrated in FIG. 5 is obtained.
In the circuit of FIG. 5, when an output terminal 170 changes from a low level to a high level, an electric current flows through four series-connected PMOS devices among those 502-504 and 511-514 connected between a power supply terminal 190 and the output terminal 170. The conduction resistance at that time is twice that of the circuit of FIG. 3. Because many PMOS devices are connected to the current path, a parasitic capacitance also increases. Increases in both the conduction resistance and the parasitic capacitance significantly reduce the circuit operation speed. A further increase in the number of choices will result in a further decrease in the operation speed.
A circuit illustrated in FIG. 6 is made by expanding the circuit of FIG. 4. In the circuit of FIG. 6, the parasitic capacitance added to the output terminal 170 increases from that of the circuit of FIG. 4 by an amount corresponding to two PMOS devices and two NMOS devices. Thus, the operation speed is reduced significantly. Further, when in the circuit of FIG. 6 the MOS transistors 601, 611 conduct to output from the output terminal 170 a signal applied to an input terminal 161, a load applied to the output terminal 170 also works as a load of a previous stage circuit that drives the input terminal 161. This means that the later stage circuit of FIG. 6 influences the operation of a previous stage circuit. Hence, if an LSI logic is to be designed by using the circuit of FIG. 6, it is necessary to consider the loads of circuits two stages ahead, making the logic design complicated. If the circuit of FIG. 6 with an inverter or the like added to the input terminals 161-164 or the output terminal 170 is treated as one circuit, this problem is eliminated. But in that case the delay time increases by an amount corresponding to one stage of inverters.